9.7-ENOB SAR ADC for Compressed Sensing

Area-efficient Low-Power 8-Bit 20-MS/s SAR ADC in 0.18μm CMOS

This paper presents the design results of the prototype IP block of the successive approximation analog-todigital converter (SAR ADC) for implementation by 0.18 um MMRF CMOS technology of UMC (Taiwan). Primarily the ADC unit was designed according to the technical requirements for the readout electronics of the silicon tracking system of the Compressed Baryonic Matter experiment at accelerator ...

C18-2 A 13b-ENOB 173dB-FoM 2nd -Order NS SAR ADC with Passive Integrators

A 53-nW 9.12-ENOB 1-kS/s SAR ADC in 0.13-μm CMOS for medical implant devices

This paper describes an ultra-low power SAR ADC for medical implant devices. To achieve the nano-watt range power consumption, an ultra-low power design strategy has been utilized, imposing maximum simplicity on the ADC architecture, low transistor count and matched capacitive DAC with a switching scheme which results in full-range sampling without switch bootstrapping and extra reset voltage. ...

Increase Dynamic Range of Sar Adcs Using Oversampling

In some previous articles general overviews of Δ-Σ and SAR (successive approximation register) ADCs, the techniques of oversampling as it relates to signal-to-noise ratio (SNR) and effective number of bits (ENOB) have been covered. The oversampling technique is most often used with the Δ-Σ ADC, but it is also useful with the SAR ADC. In this article we will dive in a bit deeper to see how this ...

Design of a 12.8 ENOB, 1 kS/s pipelined SAR ADC in 0.35-mu m CMOS

This paper presents a 15-bit, two-stage pipelined successive approximation register (SAR) analog-to-digital converter (ADC) suitable for low-power, cost-effective sensor readout circuits. The use of aggressive gain reduction in the residue amplifier combined with a suitable capacitive array DAC topology in the second stage simplifies the design of the operational transconductance amplifier (OTA...